1. Technical Field
Various embodiments generally relate to a semiconductor memory system, and more particularly, to a semiconductor memory system including a memory apparatus and a controller.
2. Related Art
In general, a memory apparatus performs write and read operations under the control of a host apparatus. The memory apparatus stores data sent from the host apparatus in the write operation and outputs stored data to the host apparatus in the read operation. The host apparatus includes a processor such as a central processing unit (CPU), a graphic processing unit (GPU) and so forth and provides to the memory apparatus signals and data for controlling the memory apparatus.
A memory controller is adopted for communication between the memory apparatus and the host apparatus. The memory controller and the memory apparatus are included in a semiconductor memory system. The memory controller converts a signal from the host apparatus into a signal that the memory apparatus may understand and process and transmit the converted signal to the memory apparatus. The memory controller converts a signal from the memory apparatus into a signal that the host apparatus may understand and process and transmit the converted signal to the host apparatus. The memory controller is essential for a semiconductor memory system operating with high speed or including a plurality of memory apparatuses.
The semiconductor memory system has a plurality of channels for data transfer. The memory apparatus receives data sent from the memory controller through a data receiver coupled to the plurality of channels. The data receiver receives data valued at ‘0’ or ‘1’ by comparing voltage level of data sent from the memory controller with level of a reference voltage, which it is important to set with accuracy for improvement of the semiconductor memory system. In a semiconductor memory system of the related art, a memory controller adjusts the reference voltage by receiving data, which the memory apparatus received, fed back from the memory apparatus.